Verilog assign statement

Signals of type wire or a similar wire like data type requires the continuous assignment of a value. For example, consider an electrical wire used to connect pieces on a breadboard. As long as the +5V battery is applied to one end of the wire, the component connected to the other end of the wire will get the required voltage.

In Verilog, this concept is realized by the assign statement where any wire or other similar wire like data-types can be driven continuously with a value. The value can either be a constant or an expression comprising of a group of signals.

Assign Syntax

The assignment syntax starts with the keyword assign followed by the signal name which can be either a single signal or a concatenation of different signal nets. The drive strength and delay are optional and are mostly used for dataflow modeling than synthesizing into real hardware. The expression or signal on the right hand side is evaluated and assigned to the net or expression of nets on the left hand side.

Delay values are useful for specifying delays for gates and are used to model timing behavior in real hardware because the value dictates when the net should be assigned with the evaluated value.

In the following example, a net called out is driven continuously by an expression of signals. i1 and i2 with the logical AND & form the expression.

If the wires are instead converted into ports and synthesized, we will get an RTL schematic like the one shown below after synthesis.

Continuous assignment statement can be used to represent combinational gates in Verilog.

The module shown below takes two inputs and uses an assign statement to drive the output z using part-select and multiple bit concatenations. Treat each case as the only code in the module, else many assign statements on the same signal will definitely make the output become X.

Assign reg variables

It is illegal to drive or assign reg type variables with an assign statement. This is because a reg variable is capable of storing data and does not require to be driven continuously. reg signals can only be driven in procedural blocks like initial and always .

Implicit Continuous Assignment

When an assign statement is used to assign the given net with some value, it is called explicit assignment. Verilog also allows an assignment to be done when the net is declared and is called implicit assignment.

Combinational Logic Design

Consider the following digital circuit made from combinational gates and the corresponding Verilog code.

Combinational logic requires the inputs to be continuously driven to maintain the output unlike sequential elements like flip flops where the value is captured and stored at the edge of a clock. So an assign statement fits the purpose the well because the output o is updated whenever any of the inputs on the right hand side change.

Hardware Schematic

After design elaboration and synthesis, we do get to see a combinational circuit that would behave the same way as modeled by the assign statement.

See that the signal o becomes 1 whenever the combinational expression on the RHS becomes true. Similarly o becomes 0 when RHS is false. Output o is X from 0ns to 10ns because inputs are X during the same time.

Click here for a slideshow with simulation example !

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The RHS can contain any expression that evaluates to a final value while the LHS indicates a variable or net to which RHS's value is being assigned.

Procedural Assignment

Procedural assignments occur within procedures such as initial, always, task , and functions are used to place values onto variables. The variable will hold the value until the next assignment to the same variable.

The value will be placed onto the variable when the simulation executes this statement during simulation time. This can be modified and controlled the way we want by using control flow statements such as if-else-if, looping , and case statement mechanisms.

Variable Declaration Assignment

An initial value can be placed onto a variable at the time of its declaration. The assignment does not have the duration and holds the value until the next assignment to the same variable happens.

NOTE: The variable declaration assignments to an array are not allowed.

If the variable is initialized during declaration and at 0 times in an initial block as shown below, the order of evaluation is not guaranteed, and hence can have either 8'h05 or 8'hee.

Continuous Assignment

This is used to assign values onto scalar and vector nets. And it happens whenever there is a change in the RHS.

It provides a way to model combinational logic without specifying an interconnection of gates and makes it easier to drive the net with logical expressions.

Whenever b or c changes its value, the whole expression in RHS will be evaluated and updated with the new value.

Net Declaration Assignment

This allows us to place a continuous assignment on the same statement that declares the net.

NOTE: Only one declaration assignment is possible because a net can be declared only once.

Procedural continuous assignment.

These are procedural statements that allow expressions to be continuously assigned to variables or nets. And these are the two types.

1. Assign deassign: It will override all procedural assignments to a variable and deactivate it using the same signal with deassign .

The value of the variable will remain the same until the variable gets a new value through a procedural or procedural continuous assignment.

The LHS of an assign statement cannot be a part-select, bit-select, or an array reference, but it can be a variable or a combination of the variables.

2. Force release: These are similar to the assign deassign statements but can also be applied to nets and variables.

The LHS can be a bit-select of a net, part-select of a net, variable, or a net but cannot be the reference to an array and bit or part select of a variable.

The force statement will override all other assignments made to the variable until it is released using the release keyword.


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Programmable Logic/Verilog Data Types

Data Values [ edit | edit source ]

Verilog has four values any signal can take:

In practice, x and z values are difficult to use in synthesis, and should typically be avoided, unless there is a very specific reason for using them.

Wire [ edit | edit source ]

Wires , specified with the wire keyword represent physical wires that carry electrical signals from one module to the next. Wires do not store any data, and they must be constantly supplied with a value or they will not contain a value. Wires may not be the target of a blocking or sequential assignment.

Wires come in one of three varieties:

Wires can be assigned a value using the assign keyword. All assign declarations are considered to be running concurrently and continuously.

In the following case, the value of a is dependent on the values of b and c . Any change in either b or c will result in an automatic and instantaneous change in the value of a .

Circular assignments cannot be made using the assign keyword, as this produces a continuous loop. In the following example, the value of a is undefined, because it depends on itself passed through combinational (i.e. asynchronous, continuously operating) logic.

For the wand and wor data types, all assignments to that wire are considered to be ports to logic gates. For instance, the following code:

Is equivalent to this code:

While it may seem like more work to use wor or wand , they can greatly simplify some complicated logic operations, and they can help to improve the readability of the code.

Reg [ edit | edit source ]

check syntax

A register , denoted with the keyword reg is a memory storage location. Registers store values without needing constant assignment, but they must be manually updated with a blocking or sequential assignment. Register values are all treated as being unsigned values, and any extension of a value into a larger register will not result in logical sign extension.

Registers can be used with the " = " and " <= "

Assignments with the "=" operator are blocking assignments, and they will be performed sequentially. Assignments with the "<=" operator are non-blocking. All non-blocking assignments in a particular code block will begin at the same time. The block will not terminate until all the non-blocking assignments have completed.

Vector [ edit | edit source ]

a vector is collection of a variables denoted with same name but with different subscripts example: [2:0]i;

Integer [ edit | edit source ]

Integer values, specified with the integer keyword are similar in function to registers, except that they are treated implicitly as signed numbers. Integer values will be logically sign-extended on assignment.

Real [ edit | edit source ]

A real number can be specified in one of the following two forms.

Parameter [ edit | edit source ]

A parameter is similar to predefined identifiers in C. It is used to declare a global constant

Arrays [ edit | edit source ]

Buses [ edit | edit source ].

Register and wire types can be specified as multi-bit buses. This assignment is made in the variable declaration using the [] operator. As an example:

This declares wire a to be a bus of 6 wires, with bit 5 ( a[5] ) being the MSB, and bit 0 ( a[0] ) being the LSB. The bit number of the LSB must be lower than the bit number for the MSB, but it needs not be zero.

Bit Selection [ edit | edit source ]

The individual wires or registers in a bus can be interfaced with directly, and subsets of the bus can be manipulated. Given the following declaration:

The following code will set a value to bit 14 of the bus:

And the following code will assign a value to the lower 8 bits of the bus:

Likewise, we can read from only part of a bus. The following code assigns the 8-bit bus b to be the upper 8 bits of the 16-bit bus a :

Part-select operators let the compiler calculate the range based on a starting point and a data-width size;

assignment data type verilog


Vrit Raval

Sep 4, 2019


There are two types of assignments in veriolg

Continuous Assignment

Procedural assignment.

A procedural assignment updates the value of register data types.


Procedural assignments are used for updating register data types and memory data types.

The expression in a blocking procedural assignment is evaluated and assigned when the statement is encountered. In a begin-end sequential statement group, execution of the next statement is blocked until the assignment is complete.

In a non-blocking procedural assignment, the expression is evaluated when the statement is encountered, and assignment is postponed until the end of the time-step. In a begin-end sequential statement group, execution of the next statement is not blocked and may be evaluated before the assignment is complete. A group of statements with a non-blocking assignment has similar functionality as a group of statements within a fork-join block.

The left-hand side of a procedural assignment should be one of the following:

When the right-hand side evaluates to a fewer bits than the left-hand side, the assignment to a reg does not sign-extend.

The evaluation of the assignment is delayed by the delay when the delay is specified before the register name. When the delay is specified before the expression, the expression is evaluated when the statement is encountered, and assigned in the time-step specified by the delay.

A continuous assignment drives a value into a net.

Continuous assignments model combinational logic. Each time the expression changes on the right-hand side, the right-hand side is re-evaluated, and the result is assigned to the net on the left-hand side.

The implicit continuous assignment combines the net declaration (see Net data type) and continuous assignment into one statement. The explicit assignment require two statements: one to declare the net (see Net data type), and one to continuously assign a value to it.

Continuous assignments are not the same as procedural continuous assignments. Continuous assignments are declared outside of procedural blocks. They automatically become active at time zero, and are evaluated concurrently with procedural blocks, module instances, and primitive instances.



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3. Data types ¶

3.1. introduction ¶.

In the Chapter 2 , we used the data-types i.e. ‘wire’ and ‘reg’ to define ‘1-bit’ & ‘2-bit’ input and output ports and signals. Also, some operators e.g. ‘and (&)’ and ‘or (|)’ etc. were discussed. In this chapter, some more information is provided on these topics.

3.2. Lexical rules ¶

Verilog is case sensitive language i.e. upper and lower case letters have different meanings. Also, Verilog is free formatting language (i.e. spaces can be added freely), but we use the python like approach to write the codes, as it is clear and readable. Lastly in Verilog, ‘//’ is used for comments; also, multiline comments can written between /* and */.

3.3. Data types ¶

Data types can be divided into two groups as follows,

3.4. Logic values ¶

Verilog has four logic values i.e. 0, 1, z and x as shown in Table 3.1 ,

3.5. Number representation ¶

The number can be represented in various format as follows, which are listed in Table 3.2 . Note that, ‘reg’ can be replaced with ‘wire’ in the table.

3.6. Signed numbers ¶

By default, ‘reg’ and ‘wire’ data type are ‘unsigned number, whereas ‘integer’ is signed number. Signed number can be defined for ‘reg’ and ‘wire’ by using ‘signed’ keywords i.e. ‘reg signed’ and ‘wire signed’ respectively as shown in Table 3.2 .

Also, ‘signed numbers’ can be converted into ‘unsigned numbers’ using ‘$unsigned()’ keyword e.g. if ‘a = -3 (i.e. 101 in 2’s complement notation)’, then ‘$unsigned(a)’ will be ‘5 (i.e. value of 101)’. Similarly, ‘unsigned numbers’ can be converted into ‘signed numbers’ using ‘signed()’ keyword.

Although, numbers can be converted from one form to another, but it should be avoided as it may results in errors which are difficult to find.

3.7. Operators ¶

In this section, various synthesizable operators of Verilog are discussed, which are shown in Table 3.3 .

3.8. Arithmetic operator ¶

Three arithmetic operators i.e. +, -, and * can be synthesized in verilog.

3.8.1. Bitwise operators ¶

Four bitwise operator are available in verilog i.e. ‘&’ (and), ‘|’ (or), ‘ ^ ‘ (xor) and ‘~’ (not). Further, we can combine these operators to define new operators e.g. ‘~&’ or ‘&~’ can be used as ‘nand’ operations etc.

3.8.2. Relational operators ¶

We already see the equality relational operation i.e. ‘==’ in section Section 2.2.4 . Further, five relational operators are defined in verilog i.e. ‘>’, ‘>=’, ‘<’, ‘<=’ and ‘!=’(not equal to).

3.8.3. Logical operators ¶

We already see the ‘and’ relational operation i.e. ‘&&’ in section Section 2.2.4 . Further, three relational operators are defined in verilog i.e. ‘||’ (or), ‘&&’ and ‘!’(negation).

3.8.4. Shift operators ¶

Verilog provides 4 types of shif operators i.e. >>, <<, >>>, <<<. Let ‘a = 1011-0011’, then we will have following results with these operators,

3.8.5. Concatenation and replication operators ¶

Concatenation operation ‘{ }’ is used to combine smaller arrays to create a large array as shown below,

Replication operator is used to repeat certain bits as shown below,

3.8.6. Conditional operator ¶

Conditional operator (?:) can be defined as follows,

Also, conditional expression can be cascaded as shown in Listing 3.1 , where 4x1 multiplexer is designed. Multiplexer is a combinational circuit which selects one of the many inputs with selection-lines and direct it to output. Fig. 3.1 illustrates the truth table for 4x1 multiplexer. Here ‘i0 - i3’ the input lines, whereas ‘s0’ and ‘s1’ are the selection line. Base on the values of ‘s0’ and ‘s1’, the input is sent to output line, e.g. if s0 and s1 are 0 then i0 will be sent to the output of the multiplexer.


Fig. 3.1 Truth table of 4x1 multiplexer

The design generated in Fig. 3.2 is exactly same as the design generated by ‘if-else statement’ which is discussed in Section 4.7 . Therefore, Fig. 3.2 is described and compared with other designs in Section 4.7 . Further, Fig. 3.3 shows the output waveform of the multiplexer which is generated by Listing 3.1 .


Fig. 3.2 Multiplexer generated by Listing 3.1


Fig. 3.3 Waveforms of Listing 3.1

3.8.7. Parameter and localparam ¶

Parameter and localparam are used to create reusable codes along with avoiding the ‘hard literals’ from the code as shown in following section.

3.8.8. localparam ¶

‘localparam’ keyword is used to defined the constants in verilog. In Listing 3.2 , N is defined in line 8 with value 3. Then this value is used in line 10 and 11. Suppose we want to change the constant value to 4. Now, we need to change it only at one place i.e. line 8 (instead of changing everywhere in the code e.g. line 10 and 11 in this example). In this way, we can remove the hard literals from the codes.

3.8.9. Parameter and defparam ¶

‘localparam’ can not be modified after declaration. But we can define the parameter in the module, which can be modified during component instantiation in structural modeling style as shown below.

Explanation Listing 3.3

In line 5, two parameters are defined i.e. ‘N’ and ‘M’. Then ports ‘a’ and ‘b’ are defined using parameter ‘N’. The always block (lines 13-19) compares ‘a’ and ‘b’ and set the value of ‘z’ to 1 if these inputs are equal, otherwise set ‘z’ to 0. Listing 3.3 Parameter ¶ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 // parameterEx.v module parameterEx #( parameter N = 2 , M = 3 //parameter ) ( input wire [ N - 1 : 0 ] a , b , output reg [ N - 1 : 0 ] z ); always @( a , b ) begin if ( a == b ) z = 1 ; else z = 0 ; end endmodule

Explanation Listing 3.4 and Listing 3.5

In line 5, ‘a’ and ‘b’ are defined as 4-bit vector. Structural modeling is used in Line 9, where parameter mapping and port mapping is performed. Note that, in line 16, ‘.N(5)’ will override the default value of N i.e. N=2 in Listing 3.3 . Also, parameter ‘M’ is not mapped, therefore default value of M will be used, which is defined in Listing 3.3 . In this way, we can remove ‘hard literals’ from the codes, which enhances the reusability of the designs. Value of the parameter ‘N’ can also be set using ‘ defparam ’ keyword, as shown in Listing 3.5 . Listing 3.4 Parameter instantiation ¶ 1 2 3 4 5 6 7 8 9 10 11 // parameterInstantEx.v module parameterInstantEx ( input wire [ 4 : 0 ] a , b , output wire [ 4 : 0 ] z ); parameterEx #(. N ( 5 )) compare4bit ( . a ( a ), . b ( b ), . z ( z )); endmodule Listing 3.5 Parameter instantiation using ‘defparam’ ¶ 1 2 3 4 5 6 7 8 9 10 11 12 // parameterInstantEx2.v module parameterInstantEx2 ( input wire [ 4 : 0 ] a , b , output wire [ 4 : 0 ] z ); parameterEx compare4bit ( . a ( a ), . b ( b ), . z ( z )); defparam compare4bit . N = 5 ; // 'defparam' to set the value of parameter endmodule

3.9. Conclusion ¶

In this chapter, we saw various data types and operators. Further Parameters and localparam are shown which can be useful in creating the reusable designs.


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Verilog: Continuous & Procedural Assignments

assignment data type verilog

Continuous Assignment

Continuous assignment is used to drive a value on to a net in dataflow modeling. The net can be a vector or scalar, indexed part select, constant bit or part select of a vector. Concatenation is also supported with scalar vector types.

Regular & Implicit Assignment

Regular continuous assignment means, the declaration of a net and its continuous assignments are done in two different statements. But in implicit assignment, continuous assignment can be done on a net when it is declared itself. In the below example, `valid` is declared as wire during the assignment. If signal name is used to the left of the continuous assignment, an implicit net declaration will be inferred. In the below code `dout` is not declared as net, but it is inferred during assignment.

Procedural Assignment

We have already seen that continuous assignment updates net, but procedural assignment update values of reg, real, integer or time variable. The constant part select, indexed part select and bit select are possible for vector reg.

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Register data types store values.


Register data types are used as variables in procedural blocks. They store logic values only (no logic strength).

The Verilog LRM defines the following register types:

A register data type must be used when the signal is on the left-hand side of a procedural assignment.

Verilog-2001 adds the ability to initialize variables at the time they are declared. The initial value assigned to the variable takes effect at simulation time zero, just as if the value had been assigned within an initial block.

Net data type , Procedural assignment

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Verilog: on left-hand side of assignment must have a variable data type

I am having trouble with combination assignment. I do not understand why I cannot use a always combination structure the set my output variables. When I use assign, I do not get the assignment error.

I thought assign and [email protected](*) both means blocking (combinational assignment)

Sugihara's user avatar

You cannot make a procedural assignment to a wire . You must make a procedural assignment to a reg , regardless of whether the always block describes sequential or combinational logic. Use the following port declarations:

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Modified: 1-Oct-2004


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